It seems that the Japanese foundry Rapidus is gearing up for strong competition with TSMC. The company has developed a panel-level packaging (PLP) prototype using a glass interposer, with plans to move towards mass production by 2028. At this week's SEMICON Japan 2025 in Tokyo, the prototype will be showcased. It replaces conventional round silicon wafers with large square glass panels, intended for use in high-performance AI packages that combine multi-chip GPUs and more than a dozen of HBM dies. This approach could reduce material waste and enable larger, denser multi-chip assemblies necessary for next-generation AI accelerators, without breaking the traditional laws of 300 mm wafer.

The company is developing 600x600 mm glass panels, which offer a significantly larger usable area than 300 mm silicon wafers and enable the production of more interposers from a single sheet. Glass substrates provide advantages in electrical performance and flatness compared to organic package materials, making them appealing for dense interconnects. However, glass also introduces new manufacturing challenges, such as fragility and potential warpage as panel sizes increase. Intel has notably discontinued its in-house development of glass substrates and has chosen to license the technology to others. The company can thus monetize its innovations, though large-scale Intel-based technology production is not anticipated until after 2030.