Delivering the next wave of chiplet innovation, Cadence has successfully taped out its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution, achieving industry-leading 64 Gbps per-lane speeds on the advanced TSMC N3P process. As the industry moves toward increasingly complex AI, high-performance computing (HPC), and data center architectures, the need for robust, high-bandwidth chiplet connectivity has never been greater. This milestone positions Cadence at the forefront of enabling scalable, energy-efficient multi-die systems for the most demanding applications.

As process nodes advance to 3 nm and below, SoC designers face the challenge of balancing optimal power, performance, and area (PPA) with the requirements of high-speed, reliable die-to-die communication. The Cadence UCIe IP solution, fully compliant with the UCIe specification, is engineered to address these challenges directly. Leveraging TSMC's innovative N3P technology, the solution delivers excellent power efficiency, allowing customers to meet aggressive energy budgets without sacrificing performance.