Intel Foundry has published a short video demonstration of its advanced packaging technologies, demoing silicon scaling beyond reticle limits of 830 mm². According to the video, Intel's Foveros 3D and EMIB-T interconnect can scale silicon to 12x reticle size, packaging up to 16 compute dies paired with 24 HBM5 memory modules in a single package. All of this will leverage Intel's 18A—including 18A-P and 18A-PT—and 14A nodes that the company is preparing for mass production and external customers.

The approach involves a sophisticated layering technique where base dies, manufactured using the 18A-PT process, incorporate backside power delivery to enhance logic density and reliability. These base dies house SRAM structures similar to Intel's "Clearwater Forest" architecture. They serve as foundations for compute tiles built on the advanced 14A/14A-E nodes, which feature second-generation RibbonFET transistors and PowerDirect technology. Foveros Direct 3D enables vertical stacking through ultra-fine pitch hybrid bonding, while EMIB-T incorporates through-silicon vias to facilitate higher bandwidth connections between chiplets. This combination achieves scalability beyond reticle limits and will support all HBM standard, including HBM4, HBM5, and future versions.