Apple's upcoming A20 chip is all set to leverage TSMC's bleeding-edge 2nm fabrication process, replete with an eye-watering price increase that is likely to end up as Apple's most expensive silicon to date.
According to Taiwan's Economic Daily, , which corresponds to an year-over-year price increase of around 80 percent relative to the cost of the A19 chip that powers Apple's current-gen iPhone 17 lineup.
This price hike is partly a function of the ongoing inflationary impulse in the memory sphere, and further bolstered by TSMC's employment of the "first-gen nanosheet transistor technology" and "ultra-high-efficiency metal interlayer capacitors" for its N2P fabrication process.
As a refresher, , also known as Gate-All-Around (GAA) technology, is a chip fabrication process where the gate surrounds the channel that is formed by stacked nanosheets, providing superior electrostatic control while allowing for a 1.2x increase in logic density.
As we reported recently, TSMC appears overwhelmed by the demand for its N2P process , which is also a contributing factor to the eye-watering increase in the cost of the A20 chip. And, Apple has reportedly reserved around half of TSMC's 2nm capacity for its own chips , worsening the situation for other prominent players such as Qualcomm and MediaTek.
For the benefit of those who might not be aware, Apple's A20 chip features a switch from InFO packaging to WMCM , where the former allowed for the integration of various components - such as DRAM - on to a single die, while the latter allows for the combination of multiple individual dies - such as the CPU, GPU, and the Neural Engine - onto a single package, providing an unprecedented level of flexibility due to the sheer number of die configurations that are available.
In fact, WMCM can allow Apple to launch the A20 chip with various configurations by employing different CPU and GPU cores. Additionally, this packaging tech allows the CPU, GPU, and the Neural Engine dies to behave individually, requesting a power draw tailored to a specific task, reducing the overall power consumption. Finally, in what should also add to the efficiency of the fabrication process, the WMCM packaging employs MUF (Molding Underfill), which helps to reduce material consumption and the number of processes.
As we noted in a dedicated post recently, TSMC's N2P process is expected to make the A20 chip's efficiency cores 'more efficient ,' allowing for improved performance without slurping on more power. The chip's GPU is also expected to feature third-gen Dynamic Cache, which should improve the allocation of on-chip memory in real time based on the workload.
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