AMD CEO Dr Lisa Su at the company's 2026 International CES event held up the next generation EPYC "Venice" enterprise processor driving the company's 2026 "Helios" AI racks powered by AMD MI455X AI GPUs. Each node in the rack features four MI455X GPUs, and one EPYC "Venice" processor that's configured with 256-core/512-thread configuration. The package features a significantly different layout of chiplets compared to current EPYC chips. It sees two slender, centralized server I/O dies built on the 4 nm node, which are flanked on either sides by no more than eight CCDs, each built on the 2 nm foundry node, and packing 32 "Zen 6" cores.

At this point we don't know if these are full-sized "Zen 6" cores that can sustain high clock speeds, or compacted "Zen 6c" cores that feature identical ISA and IPC, but at lower maximum clock speeds. Each "Venice" package features a 16-channel DDR5 memory interface (32 sub-channels), which explains why AMD probably needed to disaggregate the sIOD into two chips that are joined at the hip using high-speed switching fabric. AMD is also expected to significantly increase the PCIe and CXL lane counts of "Venice" over the current-generation to support those four AI GPUs, DPUs, and 800G NICs.