Interesting details regarding Intel's upcoming "Diamond Rapids" Xeon 7 processor family have turned up in mid-to-late December patch notes. At the time, Team Blue's Linux team discussed the nature of the chipmaker's next-gen server-grade CPU series. When comparing the "Diamond Rapids" (DMR) design to a predecessor—"Sapphire Rapids" (SPR)—the engineers outlined several key differences and new additions. On a basic level, the two generations depend on discovery tables for uncore enumeration, but the plucky newcomer could feature: "two Integrated I/O and Memory Hub (IMH) dies, which are separate from the compute tile (CBB) dies. Each 'Core Building Block' (CBB) die and each IMH die has its own dedicated discovery table." Elaborating further, Intel's second bullet point notes that: "unlike prior CPUs that retrieve the global discovery table portal exclusively through either PCI or MSR, 'Diamond Rapids' uses PCI for IMH PMON discovery and MSR for CBB PMON discovery."

InstLatX64 has weighed in on last month's "insightful" Linux kernel patch updates. They propose that "Diamond Rapids" goes even further than "Clearwater Forest" (a next-gen efficiency-focused Xeon 6+ product line ), due to its IMC being placed on the base tile. Within a lengthy list of new PMON (Performance Monitor) types, internal correspondence discloses support for PCIe 6.0—a very new standard, that was supposed to launch at some point last year. Last we heard, Intel's "Diamond Rapids" Xeon 7 lineup is expected to launch later this year, but with a reduced product lineup . At the time, 8-channel variants were cut, with 16-channel SKUs becoming the basis of the family's entire stack.