The standard CPU complex die (CCD) chiplet based on AMD's next-generation "Zen 6" microarchitecture is poised to feature a 50% increase in CPU core counts. This would be the first time that AMD has increased core-counts of its CCDs containing full-sized CPU cores capable of sustaining high clock speeds. It had developed CCDs with high core counts using compacted cores with lower clock speed limits until now. The standard "Zen 6" CCD is expected to come with a similar die-size to the current "Zen 5" CCD, with a rumored die size of 76 mm², which is slightly larger than the 71 mm² of the "Zen 5" CCD.

The "Zen 6" CCD is expected to pack 12 CPU cores, all part of a single CPU core complex (CCX). All twelve cores share a 48 MB L3 cache. Both the CPU core counts and L3 cache size hence see a 50% increase over "Zen 5." AMD is building the "Zen 6" CCD on TSMC N2 (2 nm nanosheet) process node, which evidently offers a massive increase in transistor densities over the current TSMC N4P (4 nm FinFET) on which the "Zen 5" CCD is made. With an eye on Intel's pivot towards a cache rebalancing in favor of large last-level caches on some of its premium Core Ultra 400 "Nova Lake-S" desktop processors, AMD is expected to give the "Zen 6" CCD full 3D V-Cache capability, and the company's next X3D processors could come with L3 caches of 144 MB per CCD for up to 288 MB of L3 cache on the desktop AM5 socket.