Intel is preparing to launch its next generation Core Ultra Series 4 "Nova Lake" processors in the second half of 2026. We have some hint on what the sizes of the Compute tiles of these chips could measure. "Nova Lake" remains a tile-based disaggregated chip, just like the current "Arrow Lake," with the most advanced foundry node being allocated only to the components that can benefit the most from it, the CPU cores. The CPU complex of the processor is located in the Compute tile, while low-power island E-cores are located on the SoC tile that's built on a slightly older foundry node.

Intel is building the Compute tile of "Nova Lake" on the TSMC N2 (2 nm nanosheet) foundry node. There will be different types of Compute tiles based on the CPU core count and cache sizes. The two most popular ones for the desktop platform will be the mainstream tile with 8P+16E core configuration and a standard L3 cache size shared among the eight P-cores and four E-core clusters. The second, more premium Compute tile type will be 8P+16E with bLLC, or big last-level cache. bLLC is an enlarged L3 cache that's estimated to be 3-4 times the size of the regular L3 cache. This is Intel's answer to AMD's 3D V-Cache. Estimates put the regular Compute tile to measure around 110 mm², while the premium variant with bLLC is estimated to measure over 150 mm². This 36% increase in die-area is entirely from the enlarged last-level cache.