Please note that this post is tagged as a rumor .
Intel Nova Lake-S has 150 mm² CPU bLLC tile
HXL is sharing some details on Intel’s next-gen desktop chip codenamed Nova Lake-S. There have been a lot of rumors and leaks in the past few days, likely because Intel has started sharing more information with partners. We also published some of these details earlier, including leaks related to the Z970 and Z990 chipsets , which were later expanded on by other leakers.
Intel’s Big Last Level Cache
The Core Ultra 400 series could, for the first time, bring direct competition to AMD’s 3D V-Cache lineup. Ryzen 9000X3D CPUs are currently leading sales charts, and they remain a strong value option for gaming. The extra cache can reduce CPU bottlenecks in many titles, which also helps when paired with mainstream DDR5 kits.
Intel has long been rumored to have an alternative in development, commonly referred to as bLLC (Big Last Level Cache). Unlike AMD’s stacked approach, this cache would reportedly be integrated into the compute tile itself rather than placed on top of it. That would increase die size. HXL now claims to have details on how this would affect an 8P + 16E configuration.
NVL 8+16 Die TSMC N2 ~110+mm2
NVL 8+16 bLLC Die TSMC N2 ~150+mm2 https://t.co/beHNikpl1O
— HXL (@9550pro) February 11, 2026
According to the post, t he standard die without bLLC is at least 110 mm², while the bLLC version increases to 150 mm², a 36% increase. It is also worth noting that this is not the only configuration being discussed. Intel is also reportedly exploring a dual compute tile design that could bring the total core count to 52, including LP cores from other tiles.
Intel Core Ultra 400 K-series SKUs with bLLC:
- 🟦Core Ultra 9: 52 cores (2x(8+16)+4 LPE), ~288 MB bLLC Dual Tile
- 🟦Core Ultra 7: 28 cores (8+16+4 LPE), ~ 144MB bLLC
AMD Ryzen 10000X3D series with 3D V-Cache
- 🟨Ryzen 9 : 24 cores (2×12) ~ 192MB 3D V-Cache Dual CCD
- 🟨Ryzen 7 : 12 cores ~ 96MB 3D V-Cache
HXL also quoted an earlier post where the same leaker mentioned the die size of AMD’s Zen 6 CCD. AMD’s next-gen Ryzen is also expected to have dual-CCD variants, but the single-CCD option may be the more important volume product. AMD is reportedly increasing CCD core count from 8 to 12 cores.
Current rumors put the bLLC cache size at 144MB per Compute Tile. This means that the dual-tile version would feature 288MB. AMD, on the other hand, is expected to increase the 3D V-Cache size from 64MB to 96MB, which means 192MB in dual-CCD variant.
Source: HXL
